View CY7C4261V-10JXC_8904172.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v 16 k / 32 k / 64 k / 128 k 9 low-voltage deep sync? fifos cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-06013 rev. *h revised december 20, 2012 features 3.3 v operation for low-power consumption and easy integration into low-voltage systems high-speed, low-power, first-in first-out (fifo) memories 16 k 9 (cy7c4261v) 32 k 9 (cy7c4271v) 64 k 9 (cy7c4281v) 128 k 9 (cy7c4291v) 0.35-micron cmos for optimum speed or power high-speed 100-mhz operation (10-ns read/write cycle times) low power ? i cc = 25 ma ? i sb = 4 ma fully asynchronous and simultaneous read and write operation empty, full, and programmable almost empty and almost full status flags output-enable (oe ) pin independent read- and write-enable pins supports free-running 50% duty cycle clock inputs width-expansion capability pin-compatible 3.3 v solu tions for cy7c4261/71/81/91 pin-compatible density upgrade within the cy7c42x1v family pb-free packages available functional description the cy7c4261/71/81/91v are high-speed, low-power fifo memories with clocked read and write interfaces. all are nine bits wide. the cy7c4261/71/81/91v ar e pin-compatible with the lower densities in the cy7c42x1v synchronous fifo family. programmable features include al most full/almost empty flags. these fifos provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. these fifos have 9-bit input and output ports that are controlled by separate clock and enable signals. the input port is controlled by a free-running clock (wclk) and two write-enable pins (wen1 , wen2/ld ). when wen1 is low and wen2/ld is high, data is written into the fifo on the rising edge of the wclk signal. while wen1 and wen2/ld are held active, data is continually written into the fifo on each wclk cycle. the output port is controlled in a similar manner by a free-running read clock (rclk) and two read-enable pins (ren1 , ren2 ). in addition, the cy7c4261/71/81/91v has an output-enable pin (oe ). the read (rclk) and write (wclk) clo cks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. clock frequencies up to 100 mhz are achievable. depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. the cy7c4261/71/81/91v provides f our status pins: empty, full, programmable almost empty, and programmable almost full. the almost empty/almost full flags are programmable to single word granularity. the programmable flags default to empty +7 and full ?7. the flags are synchronous, that is, they change state relative to either the read clock (rclk) or the write clock (wclk). when entering or exiting the empty and almost empty states, the flags are updated exclusively by the rclk. the flags denoting almost full, and full states are updated exclusively by wclk. the synchronous flag architecture guarantees that the flags maintain their status for at least one cycle. all configurations are fabr icated using an advanced 0.35 ? cmos technology. input esd protection is greater than 2001 v, and latch-up is prevented by the use of guard rings. selection guide 7c4261/71/81/91v-10 7c4261/91v-15 unit maximum frequency 100 66.7 mhz maximum access time 8 10 ns minimum cycle time 10 15 ns minimum data or enable setup 3.5 4 ns minimum data or enable hold 0 0 ns maximum flag delay 8 10 ns active power supply current (i cc1 ) commercial 25 25 ma industrial ? 30 cy7c4261v cy7c4271v cy7c4281v cy7c4291v density 16 k x 9 32 k 9 64 k 9 128 k 9 package 32-pin plcc 32-pin pl cc 32-pin plcc 32-pin plcc
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 2 of 22 tristate output register read control flag logic write control write pointer read pointer reset logic input register flag program register d 0?8 rclk q 0?8 wen1 wclk rs oe dual port wen2/ld ren1 ren2 ef pae paf ff ram array 16 k/32 k x 9 64 k/128 k logic block diagram
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 3 of 22 contents pin configuration ............................................................. 4 pin definitions .................................................................. 4 architecture ...................................................................... 5 resetting the fifo ............................................................ 5 fifo operation ................................................................. 5 programming .................................................................... 5 width-expansion configuration ...................................... 7 flag operation .................................................................. 7 maximum ratings ............................................................. 8 switching characteristics .............................................. 10 switching waveforms .................................................... 11 write cycle timing .................................................... 11 read cycle timing .................................................... 11 reset timing .............................................................. 12 first data word latency after reset with read and write 13 full flag timing . ........................................................ 15 programmable almost empty flag timing ................ 15 programmable almost full flag timing .................... 16 write programmable registers ................................. 16 read programmable registers .............. ........... ........ 17 ordering code definition .... ....................................... 18 ordering information ...................................................... 18 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 document history page ................................................. 21 sales, solutions, and legal information ...................... 22 worldwide sales and design s upport ......... .............. 22 products .................................................................... 22 psoc solutions ......................................................... 22
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 4 of 22 plcc d 1 d 0 rclk v cc d 8 d 7 d 6 d 5 d 4 d 3 gnd wclk wen2/ld q 8 q 7 d 2 paf pae 5 6 7 8 9 10 11 12 13 ren1 oe ren2 4321 3130 32 21 22 23 24 27 28 29 25 26 14 15 16 17 18 19 20 q 6 q 5 wen1 rs ff q 0 q 1 q 2 q 3 q 4 ef top view cy7c4261v cy7c4271v cy7c4281v cy7c4291v pin configuration pin definitions pin no. signal name description i/o description 1?6, 30?32 d 0 ? 8 data inputs i data inputs for 9-bit bus. 16?24 q 0 ? 8 data outputs o data outputs for 9-bit bus. 28 wen1 write enable 1 i the only write enable when device is configured to have programmable flags. data is written on a low-to-high transition of wclk when wen1 is asserted and ff is high. if the fifo is configur ed to have two write enables, data is written on a low-to-high transition of wclk when wen1 is low and wen2/ld and ff are high. 26 wen2/ld dual mode pin write enable 2 i if high at reset, this pin oper ates as a second write enable. if low at reset, this pin operates as a control to write or read the programmable flag offsets. wen1 must be low and wen2 must be high to write data into the fifo. data will not be written into the fifo if the ff is low. if the fifo is configured to have programmable flags, wen2/ld is held low to write or read the programmable flag offsets. load 10, 12 ren1 , ren2 read enable inputs i enables the device for read operation. both ren1 and ren2 must be asserted to allow a read operation. 27 wclk write clock i the rising edge clocks data into the fifo when wen1 is low and wen2/ld is high and the fifo is not full. when ld is asserted, wclk writes data into the programmable flag-offset register. 11 rclk read clock i the risi ng edge clocks data out of the fifo when ren1 and ren2 are low and the fifo are not empty. when wen2/ld is low, rclk reads data out of the programmable flag-offset register. 14 ef empty flag o when ef is low, the fifo is empty. ef is synchronized to rclk. 15 ff full flag o when ff is low, the fifo is full. ff is synchronized to wclk. 8pae programmable almost empty o when pae is low, the fifo is almost empt y based on the almost empty offset value programmed into the fifo. pae is synchronized to rclk. 7paf programmable almost full o when paf is low, the fifo is almost full based on the almost full offset value programmed into the fifo. paf is synchronized to wclk. 29 rs reset i resets device to empty condition. a re set is required before an initial read or write operation after power-up. 13 oe output enable i when oe is low, the fifo?s data outputs drive the bus to which they are connected. if oe is high, the fifo?s outputs are in high z (high-impedance) state.
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 5 of 22 architecture the cy7c4261/71/81/91v consists of an array of 16 k, 32 k, 64 k, or 128 k words of nine bits each (implemented by a dual-port array of sram cells), a read pointer, a write pointer, control signals (rclk, wclk, ren1 , ren2 , wen1 , wen2, rs ), and flags (ef , pae , paf , ff ). resetting the fifo upon power-up, the fifo must be reset with a reset (rs ) cycle. this causes the fifo to enter the empty condition signified by ef being low. all data outputs (q 0?8 ) go low t rsf after the rising edge of rs . in order for the fifo to reset to its default state, the user must not read or write while rs is low. all flags are guaranteed to be valid t rsf after rs is taken low. fifo operation when the wen1 signal is active low, wen2 is active high, and ff is active high, da ta present on the d 0?8 pins is written into the fifo on each rising edge of the wclk signal. similarly, when the ren1 and ren2 signals are active low and ef is active high, data in the fifo memory will be presented on the q 0-8 outputs. new data will be presented on each rising edge of rclk while ren1 and ren2 are active. ren1 and ren2 must set up t ens before rclk for it to be a valid read function. wen1 and wen2 must occur t ens before wclk for it to be a valid write function. an output enable (oe ) pin is provided to three-state the q 0?8 outputs when oe is asserted. when oe is enabled (low), data in the output register will be available to the q 0-8 outputs after t oe . if devices are cascaded, the oe function will only output data on the fifo that is read enabled. the fifo contains overflow circui try to disallow additional writes when the fifo is full, and underflow circuitry to disallow additional reads when the fifo is empty. an empty fifo maintains the data of the last valid read on its q 0-8 outputs even after additional reads occur. write enable 1 (wen1 ) . if the fifo is configured for programmable flags, write enable 1 (wen1 ) is the only write enable control pin. in this configuration, when write enable 1 (wen1 ) is low, data can be loaded into the input register and ram array on the low-to-high transition of every write clock (wclk). data is stored is the ram array sequentially and independently of any on-going read operation. write enable 2/load (wen2/ld ) . this is a dual-purpose pin. the fifo is configured at reset to have programmable flags or to have two write enables, which allows for depth expansion. if write enable 2/load (wen2/ld ) is set active high at reset (rs = low), this pin operates as a second write enable pin. if the fifo is configured to have two write enables, when write enable (wen1 ) is low and write enable 2/load (wen2/ld ) is high, data can be loaded into the input register and ram array on the low-to-high transition of every write clock (wclk). data is stored in the ram array sequentially and independently of any on-going read operation. programming when wen2/ld is held low during reset, this pin is the load (ld ) enable for flag offset programming. in this configuration, wen2/ld can be used to access the four 9-bit offset registers contained in the cy7c4261/71/81/91v for writing or reading data to these registers. when the device is configured for programmable flags and both wen2/ld and wen1 are low, the first low-to-high transition of wclk writes data from the data inputs to the empty offset least significant bit (lsb) register. the second, third, and fourth low-to-high transitions of wclk store data in the empty offset most significant bit (msb) register, full offset lsb register, and full offset msb register, respectively, when wen2/ld and wen1 are low. the fifth low-to-high transition of wclk while wen2/ld and wen1 are low writes dat a to the empty lsb register again. figure 1 shows the registers sizes and default values for the various device types. 64k x 9 8 0 8 0 8 0 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h (msb) 7 7 7 8 0 8 0 8 0 8 0 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h (msb) (msb) 7 7 128k x 9 8 0 (msb) 7 default value = 000h default value = 000h default value = 000h default value = 000h 16 k 8 0 8 0 8 0 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h (msb) 7 5 7 8 0 8 0 8 0 0 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h (msb) (msb) 7 7 32 k x 9 0 (msb) default value = 000h default value = 000h default value = 000h default value = 000h 6 8 5 8 6 figure 1. offset register location and default values x9
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 6 of 22 it is not necessary to write to all the offset registers at one time. a subset of the offset registers can be written; then by bringing the wen2/ld input high, the fifo is returned to normal read and write operation. the next time wen2/ld is brought low, a write operation stores data in the next offset register in sequence. the contents of the offset re gisters can be read to the data outputs when wen2/ld is low and both ren1 and ren2 are low. low-to-high transitions of rclk read register contents to the data outputs. writes and reads should not be performed simultaneously on the offset registers. programmable flag (pae , paf ) operation whether the flag offset regist ers are programmed as described in ta b l e 1 or the default values are used, the programmable almost-empty flag (pae ) and programmable almost-full flag (paf ) states are determined by their corresponding offset registers and the difference between the read and write pointers. the number formed by the empty offset least significant bit register and empty offset most significant bit register is referred to as n and determines the operation of pae . pae is synchronized to the low-to-high transition of rcl k by one flip-flop and is low when the fifo contains n or fewer unread words. pae is set high by the low-to-high transition of rclk when the fifo contains (n+1) or greater unread words. the number formed by the full offset least significant bit register and full offset most significant bit register is referred to as m and determines the operation of paf . paf is synchronized to the low-to-high transition of wclk by one flip-flop and is set low when the number of unread words in the fifo is greater than or equal to cy7c4261v (16k ? m), cy7c4271v (32k ? m), cy7c4281v (64k ? m) and cy7c4291v (128k ? m). paf is set high by the low-to-high transition of wclk when the number of available memory locations is greater than m. table 1. writing the offset registers [1] ld wen wclk selection 00 0 1 no operation 1 0 write into fifo 1 1 no operation empty offset (lsb) empty offset (msb) full offset (lsb) full offset (msb) table 2. status flags number of words in fifo ff paf pae ef cy7c4261v cy7c4271v cy7c4281v cy7c4291v 0000 hhll 1 to n [2] 1 to n [2] 1 to n [2] 1 to n [2] hh l h (n + 1) to (16384 ? (m + 1)) (n + 1) to (32768 ? (m + 1)) (n + 1) to (65536 ? (m + 1)) (n + 1) to (131072 ? (m + 1)) h h h h (16384 ? m) [3] to 16383 (32768 ? m) [3] to 32767 (65536 ? m) [3] to 65535 (131072 ? m) [3] to 131071 h l h h 16384 32768 65536 131072 l l h h notes 1. the same selection sequence applies to reading from the registers. ren1 and ren2 are enabled and a read is performed on the low-to-high transition of rclk. 2. n = empty offset (n = 7 default value). 3. m = full offset (m = 7 default value).
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 7 of 22 width-expansion configuration word width may be increased simply by connecting the corresponding input controls signals of multiple devices. a composite flag should be created for each of the end-point status flags (ef and ff ). the partial status flags (pae and paf ) can be detected from any one device. figure 2 demonstrates a 18-bit word width by using two cy7c42x1vs. any word width can be attained by adding additional cy7c42x1vs. when the cy7c42x1v is in a wi dth-expansion configuration, the read enable (ren2 ) control input can be grounded (see figure 2 ). in this configuration, the write enable 2/load (wen2/ld ) pin is set to low at reset so that the pin operates as a control to load and read the programmable flag offsets. flag operation the cy7c4261/71/81/91v devices provide five flag pins to indicate the condition of the fi fo contents. empty, full, pae , and paf are synchronous. full flag the full flag (ff ) will go low when the device is full. write operations are inhibited whenever ff is low regardless of the state of wen1 and wen2/ld . ff is synchronized to wclk, i.e., it is exclusively updated by each rising edge of wclk. empty flag the empty flag (ef ) will go low when the device is empty. read operations are inhibited whenever ef is low, regardless of the state of ren1 and ren2 . ef is synchronized to rclk, that is, it is exclusively updated by each rising edge of rclk. ff ff ef ef write clock (wlck) full flag (ff )# 1 cy7c4261v 9 18 data reset (rs) 9 reset (rs ) read clock (rclk) read enable 1 (ren1 ) output enable (oe ) programmable (pae ) empty flag (ef ) #1 9 data out (q) 918 read enable 2 (ren2 ) empty flag (ef ) #2 full flag (ff )# 2 read enable 2 (ren2 ) cy7c4271v cy7c4281v cy7c4291v cy7c4261v cy7c4271v cy7c4281v cy7c4291v figure 2. block diagram of 16 k / 32 k / 64 k / 128 k 9 low-voltage deep sync fifo memory used in a width-expansion configuration in (d) write enable (wen1 ) write enable 2/load (wen2/ld ) programmable (paf )
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 8 of 22 maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature .................................. ?65 c to +150 c ambient temperature with power applied ... ?55 c to +125 c supply voltage to ground potenti al ...............?0.5 v to +3.6 v dc voltage applied to outputs in high-z state ..................................... ?0.5 v to v cc + 0.5 v dc input voltage .................................. ?0.5 v to v cc + 0.5 v output current into outputs (low) .............................. 20 ma static discharge voltage........................................... > 2001 v (per mil-std-883, method 3015) latch-up current ..................................................... > 200 ma operating range range ambient temperature v cc [4] commercial 0 c to +70 c 3.3 v ? 300 mv industrial ? 40 c to +85 c 3.3 v ? 300 mv electrical characteristics over the operating range parameter description test conditions 7c4261/71/81/91v-10 7c4261/91v-15 unit min max min max v oh output high voltage v cc = min., i oh = ? 1.0 ma v cc = 3.0 v, i oh = ? 2.0 ma 2.4 ? 2.4 ? v v ol output low voltage v cc = min., i ol = 4.0 ma v cc = 3.0 v, i ol = 8.0 ma ?.04?0.4v v ih input high voltage ? 2.0 v cc 2.0 v cc v v il input low voltage ? ? 0.5 0.8 ? 0.5 0.8 v i ix input leakage current v cc = max. ? 10 +10 ? 10 +10 ? a i ozl i ozh output off, high z current oe ?? v ih , v ss < v o < v cc ? 10 +10 ? 10 +10 ? a i cc1 [5] active power supply current ? commercial ? 25 ? 25 ma industrial ? ? ? 30 ma i sb [6] average standby current ? commercial ? 4 ? 4 ma industrial ? ? ? 4 ma capacitance parameter [7] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3 v 5pf c out output capacitance 7 pf notes 4. v cc range for commercial ?10 ns is 3.3 v 150 mv. 5. input signals switch from 0 v to 3 v with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum freq uency of 20 mhz, while data inputs switch at 10 mhz. outputs are unloaded. 6. all inputs = v cc ? 0.2 v, except wclk and rclk (which are at frequency = 0 mhz). all outputs are unloaded. 7. tested initially and after any design or process changes that may affect these parameters.
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 9 of 22 ac test loads and waveforms (?15 and ?25) [8, 9] ac test loads and waveforms (?10) including 3.0 v 3.3 v output r1 = 330 ? r2=510 ? c l jig and scope gnd 90% 10% 90% 10% ? 3ns ? 3 ns output 2.0 v equivalent to: th venin equivalent 200 ? all input pulses notes 8. c l = 30 pf for all ac parameters except for t ohz . 9. c l = 5 pf for t ohz . 3.0v gnd 90% 10% 90% 10% ? 3ns ? 3 ns all input pulses i/o 50 ? v cc/2 z0 = 50 ?
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 10 of 22 switching characteristics over the operating range parameter description 7c4261/71/81/91v-10 7c4261/91v-15 unit min max min max t s clock cycle frequency ? 100 ? 66.7 mhz t a data access time 2 8 2 10 ns t clk clock cycle time 10 ? 15 ? ns t clkh clock high time 4.5 ? 6 ? ns t clkl clock low time 4.5 ? 6 ? ns t ds data set-up time 3.5 ? 4 ? ns t dh data hold time 0 ? 0 ? ns t ens enable set-up time 3.5 ? 4 ? ns t enh enable hold time 0 ? 0 ? ns t rs reset pulse width [10] 10 ? 15 ? ns t rss reset set-up time 8 ? 10 ? ns t rsr reset recovery time 8 ? 10 ? ns t rsf reset to flag and output time ? 10 ? 15 ns t olz output enable to output in low z [10] 0?0 ?ns t oe output enable to output valid 3 7 3 10 ns t ohz output enable to output in high z [11] 373 8ns t wff write clock to full flag ? 8 ? 10 ns t ref read clock to empty flag ? 8 ? 10 ns t paf clock to programmable almost-full flag ? 8 ? 10 ns t pae clock to programmable almost-full flag ? 8 ? 10 ns t skew1 skew time between read clock and write clock for empty flag and full flag 5?6 ?ns t skew2 skew time between read clock and write clock for almost-empty flag and almost-full flag 10 ? 15 ? ns notes 10. pulse widths less than minimum values are not allowed. 11. values guaranteed by design, not currently tested.
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 11 of 22 switching waveforms figure 3. write cycle timing figure 4. read cycle timing t clkh t clkl no operation t ds t skew1 t ens wen1 t clk t dh t wff t wff t enh wclk d 0 ?d 17 ff ren1 , ren2 rclk no operation wen2 (if applicable) [12] ren1 , ren2 t clkh t clkl no operation t skew1 wen1 t ckl t ohz t ref t ref rclk q 0 ?q 17 ef wclk oe t oe t ens t olz t a t enh valid data wen2 [13] notes 12. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk rising edge. 13. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high during the current clock cycle. it the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then ef may not change state until the next rclk rising edge.
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 12 of 22 figure 5. reset timing [14] notes 14. the clocks (rclk, wclk) can be free-running during reset. 15. after reset, the outputs will be low if oe = 0 and three-state if oe =1. 16. holding wen2/ld high during reset will make the pin act as a second enable pin. holding wen2/ld low during reset will make the pin act as a load enable for the programmable flag offset registers. switching waveforms (continued) t rs t rsr q 0 ? q 8 rs t rsf t rsf t rsf oe = 1 oe=0 ren1 , ren2 ef ,pae ff , paf t rss t rsr t rss t rsr t rss wen2/ld wen1 [16] [15]
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 13 of 22 figure 6. first data word latency after reset with read and write notes 17. when t skew1 > minimum specification, t frl (maximum) = t clk + t skew2 . when t skew1 < minimum specification, t frl (maximum) = either 2*t clk + t skew1 or t clk + t skew1 . the latency timing applies only at the empty boundary (ef = low). 18. the first word is available the cycle after ef goes high, always. switching waveforms (continued) d 0 t skew1 wen1 wclk q 0 ?q 8 ef ren1 , ren2 oe t oe t ens t olz t ds rclk t ref t a t frl d 1 d 2 d 3 d 4 d 0 d 1 d 0 ?d 8 t a wen2 (if applicable) [17] [18] (first valid write)
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 14 of 22 figure 7. empty flag timing switching waveforms (continued) data write 2 data write 1 t ens t skew1 data in output register wen1 wclk q 0 ?q 8 ef ren1 , ren2 oe t ds t enh rclk t ref t a t frl d 0 ?d 8 data read t skew 1 t frl t ref t ds t ens t enh t ens wen2 (if applicable) t enh t ens t enh t ref low [19] [19] note 19. when t skew1 > minimum specification, t frl (maximum) = t clk + t skew2 . when t skew1 < minimum specification, t frl (maximum) = either 2*t clk + t skew1 or t clk + t skew1 . the latency timing applies only at the empty boundary (ef = low).
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 15 of 22 figure 8. full flag timing figure 9. programmable almost empty flag timing notes 20. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk rising edge. 21. t skew2 is the minimum time between a rising wclk and a rising rclk edge for pae to change state during that clock cycle. if the time between the edge of wclk and the rising rclk is less than t skew2 , then pae may not change state until the next rclk. 22. pae offset = n. 23. if a read is performed on this rising edge of the read clock, there will be empty + (n ? 1) words in the fifo when pae goes low. switching waveforms (continued) q 0 ?q 8 ren1 , ren2 wen1 wen2 (if applicable) d 0 ?d 8 next data read data write no write data in output register ff wclk oe rclk t a data read t skew1 t ds t ens t enh t wff t a t skew1 t ens t enh t wff data write no write t wff low [20] [20] t enh wclk pae rclk t clkh t ens t clkl t ens t pae n + 1 words in fifo t enh t ens t enh t ens t pae ren1 , ren2 wen1 wen2 (if applicable) t skew2 [21] 22 23
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 16 of 22 figure 10. programmable almost full flag timing figure 11. write programmable registers notes 24. if a write is performed on this rising edge of the write clock, there will be full ? (m ? 1) words of the fifo when paf goes low. 25. paf offset = m. 26. 16 k ?? m words for cy7c4261v, 32 k ? m words for cy7c4271v, 64 k ? m words for cy7c4281v, and 128 k ? m words for cy4291v. 27. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge for paf to change during that clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew2 , then paf may not change state until the next wclk. switching waveforms (continued) note note t enh wclk paf rclk t clkh t ens ( full - m) words in fifo t clkl t ens full ?? (m+1) words in fifo t enh t ens t enh t ens t paf ren1, ren2 wen1 wen2 (if applicable) t skew2 t paf [26] [27] 24 25 t enh wen2/ld wclk t clkh t ens t clkl pae offset lsb d 0 ?d 8 wen1 t ens paf offset msb t clk t ds t dh pae offset msb paf offset lsb
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 17 of 22 figure 12. read programmable registers switching waveforms (continued) paf offset msb paf offset lsb t enh wen2/ld rclk t clkh t ens t clkl pae offset lsb q 0 ?q 15 ren1, ren2 t ens pae offset msb t clk unknown t a
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 18 of 22 ordering code definitions ordering information 16 k 9 low-voltage deep sync fifo speed (ns) ordering code package name package type operating range 10 CY7C4261V-10JXC j65 32-pin pb-free plastic leaded chip carrier commercial 15 cy7c4261v-15jxc j65 32-pin pb-free plastic leaded chip carrier commercial 64 k 9 low-voltage deep sync fifo 10 cy7c4281v-10jxc j65 32-pin pb-free plastic leaded chip carrier commercial 128 k 9 low-voltage deep sync fifo 15 cy7c4291v-15jxc j65 32-pin pb-free plastic leaded chip carrier commercial cy 7 4 2 - x 1 company code: cy = cypress v xx j x x family: sram fifo width: x9 depth: 6 = 16 k; 7 = 32 k 8 = 64 k; 9 = 128 k x9 3.3 v 10 ns / 15 ns plcc pb-free (rohs compliant) temperature range: c= commercial
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 19 of 22 package diagram figure 13. 32-pin pb-free plastic leaded chip carrier j65, 51-85002 51-85002 *d
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 20 of 22 acronyms document conventions units of measure table 3. acronyms used acronym description cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory tsop thin small outline package we write enable table 4. units of measure symbol unit of measure ns nanosecond vvolt a microampere ma milliampere pf picofarad c degree celsius wwatt
cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v document number: 38-06013 rev. *h page 21 of 22 document history page document title: cy7c4261v/cy7c4271v/cy7c4281v/cy7c4291v 16 k / 32 k / 64 k / 128 k 9 low-voltage deep sync? fifos document number: 38-06013 revision ecn orig. of change submission date description of change ** 106474 szv 09/15/01 changed spec number from 38-00656 to 38-06013 *a 127858 fsg 09/04/03 changed: t skew2 to t skew1 in switching waveforms ?empty flag timing? diagram fixed flag timing diagram in switching waveforms section *b 386127 esh see ecn added pb-free logo to top of front page added cy7c4291v-15jxc, cy7c91v-10jxc, cy7c4281v-10jxc, cy7c4271v-10jxc, CY7C4261V-10JXC, cy7c4261v-15jxc to ordering information. *c 2896378 rame 03/19/2010 removed inactive parts from ordering information and updated package diagram. *d 2906525 rame 04/07/2010 removed inactive part from ordering information table. *e 3069396 admu 10/22/2010 corrected data in programmable flag (pae , paf ) operation: a) paf is synchronized to the low-to-high transition of rclk by one flip-flop and is low when the fifo contains n or fewer unread words. changed paf to pae . b) pae is synchronized to the low-to-high tr ansition of wclk by one flip-flop and is set low when the number of unrea d words in the fifo is greater than or equal to cy7c4261 (16k-m) and cy7c4271 (32k-m). changed pae to paf . added acronyms , document conventions , and ordering code definitions . *f 3210221 admu 03/25/2011 removed cy7c4271v-10jc part from ordering information table. *g 3325014 admu 07/22/2011 removed speed bin ?25. updated package diagram to *d revision. *h 3847934 admu 12/20/2012 updated ordering information (updated part numbers).
document number: 38-06013 rev. *h revised december 20, 2012 page 22 of 22 deep sync is a trademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c4261v/cy7c4271v cy7c4281v/cy7c4291v ? cypress semiconductor corporation, 2005-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

▲Up To Search▲

Price & Availability of CY7C4261V-10JXC

	To Download CY7C4261V-10JXC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .